minimig-mist
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rkrajnc
Cache clear flag possible issue
https://github.com/rkrajnc/minimig-mist/blob/da69f6ec45f9956f1df56f0a9a7f4a062c9b726e/rtl/sdram/cpu_cache_new.v#L214
CACR[3] is write-only bit, so CPU cannot read the last state, thus if it will write 1 second and more times it won't trigger the clear since internally it's 1 already. Isn't?
I didn't implement this correctly in the TG68 code - the C & CE bits should not be latched, it should be just a pulse that should signal the cache to clear itself.
Ok. At least i understood it correctly :) I'm trying to replace TG68 core with 68EC30 core i've found. Unfortunately Minimig uses some specific to TG68 signals making hard to port standard CPU core.
Can you share the 030 core, I can take a look at it and see if anything can be done quickly?
Sure! Would be good if you will help. It's from Suska project: https://download.experiment-s.de/Configware/rtl/vhdl.zip Inside you can find 68EC30: vhdl\68K30L
CACR register is not implemented (other MOVEC registers are implemented), but should be not so hard to add. What harder is to re-create cpustate signal. I found something similar in 68EC030, but not sure if it will resemble the same timings.
Overall 68K30L looks like more complete than TG68K.
You will need to add 32bit->16bit bus glue logic which you can get from here: https://github.com/terriblefire/tf530 It has RTL code, so pretty much can be used as-is in minimig.
