riscv-isa-sim
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riscv-software-src
Spike, a RISC-V ISA Simulator
Hello team, I have added the trigonometric instructions on riscv-gnu-toolchain. Now I am specifically looking for the steps required/process to compile my workload in Spike and Gem5 with these newly...
Adding support for additional vector crypto extensions (fast track draft): - Zvbc32e extension: 32-bit `vcmul.[vv,vx]` and `vclmulh.[vv,vx]` - Zvkgs extension: `vgmul.vs` and `vghsh.vs` Those new extensions requires new opcodes (in...
I found an issue in commit https://github.com/riscv-software-src/riscv-isa-sim/commit/20a735414863ffaa5525bc5bac04f6bc256e6f07. Sorry for the mistake. The logging value is the read value on updating. The read value of mip depends on the value of...
In readme.md In a separate shell run OpenOCD with the appropriate configuration file: $ cat spike.cfg adapter driver remote_bitbang remote_bitbang host localhost remote_bitbang port 9824 ... "remote_bitbang host localhost" should...
It is a nice feature to have Ctrl-C for entering debug mode and using command `rs` for returning normal running. However, how can I deliberately send a signal by Ctrl-C...
HI Guys, I am trying to load elf, to SPIKE htif memory , by proving the path of elf file, and not calling SPIKE , instead, calling sim_t in my...
Spec states that > For a given supported fractional LMUL setting, implementations must support SEW settings between SEWmin and LMUL * ELEN, inclusive. So, for ELEN=64 and LMUL=1/8 the the...
Not yet frozen, but in a pretty stable state. See https://github.com/riscv/riscv-dot-product
As per the spec for Zve*f extension floating point operands with EEW=64 are not supported: > All Zve* extensions support all vector permutation instructions (Section Section 31.16), except that Zve32x...
These are the changes: - Zvkg (vghsh.vv, vgmul.vv) - vl must be a multiple of EGS=4. (spec p.13) - Check alignment of vd, vs1, vs2 with lmul - Zvksh (vsm3c.vi,...
