riscv-isa-sim
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riscv-software-src
Spike, a RISC-V ISA Simulator
I am executing one executable file on RISCV Linux (Spike Simulator), I want to know how many instructions executed for particular executable. Thanks In Advance
Hello, Can someone give me a guideline or references to: (A) trigger or request an interrupt while executing instruction in the interaction mode? or, (B) give Spike where (PC addresses)...
``` int true_exp = exp - 1023; int shift = true_exp - 52; /* Restore implicit bit. */ frac |= 1ull = 64) { /* The fraction is shifted out...
If I understand correctly from spec, mtinst is a WARL register that can be written by machine mode. However, reading it in machine mode when the H extension is not...
While trying to implement type 6 trigger (mcontrol6) with load bit enabled according to the debug spec 1.0 but spike doesnt seem to support (still using 0.13 version) . tinfo.version...
To test a RISC-V core with only Machine mode implemented, I require spike to run with M privilege mode. Building spike as normal with the config options `--prefix=$RISCV --with-isa=rv32imf` and...
The read() call may be interrupted by a signal, resulting in an EINTR error. In this case, read() will return -1 and set errno to EINTR. This is a common...
Can sfence.vma instruction be executed in supervisor mode? I think both 'S' and 'M' modes are possible, but spike doesn't support it in 'M' mode. Also, it doesn't work even...
In Spike's double trap check for VS/S mode, the current code accesses `state.nonvirtual_sstatus` in VS mode and `state.sstatus` in S mode. [processor.cc#L447-L453](https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/processor.cc#L447-L453) I think this reverses the intended access to...
- OpenOCD v0.11.0-2 released Oct 17, 2021 or later supports address translation. - we can use pk (and system calls) - we can use stack. - we don't need a...
