riscv-isa-sim
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riscv-software-src
Spike, a RISC-V ISA Simulator
Current spike implementation erroneously assumes that a maximum physical address is limited to (1
Does the [release v1.1.0](https://github.com/riscv-software-src/riscv-isa-sim/releases/tag/v1.1.0) support dumping memory signature? There is no such option in this version of Spike binary: https://github.com/riscv-software-src/riscv-isa-sim/blob/530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike.cc#L18-L77 However, the host interface seems to support it: https://github.com/riscv-software-src/riscv-isa-sim/blob/1767a27ad4cf8f9eb1a30d9d9a2495477071339f/fesvr/htif.cc#L150-L155
Hi yall, I'm trying to modify spike to directly control the fetched instruction data, starting from the very first instruction execution. This has been a bit difficult due to a...
Hi, I recently developped a RISC-V OoO core and used Spike as a reference model in the verilator simulation of the hardware core. Got the simulation to keep spike and...
Hi, I want to run a OpenMP code on Spike. I believe I need a Linux on Spike in SMP mode. So, could someone please help me with how I...
All ! Considering that Spike is the Golden Model of the risc-v ISA (incl. extensions), Considering how valuable it is wrt. the verification of our designs, Considering how useful it...
Im not sure if I can do this with spike. I make a hello world and compile in 32 bits like you see below and I tried to measure the...
Is spike compatible for RHEL machines?
When I enter 0xc5f957, it outputs ```vsetvli s2, a1, e16, m, tu, mu```. (code)[https://github.com/riscv-software-src/riscv-isa-sim/blob/master/disasm/disasm.cc#L439] But I didn't find a description about the fourth parameter ```m``` in the rfc of rvv.
