Ross Daly

Results 98 issues of Ross Daly

Print out how long each pass took in verbose mode

verilog inlining code sometimes hangs.

I have not been able to isolate an example as it happens randomly and on linux. Will update with a concrete way to recreate.

Update RAM generator to have a read latency parameter

1 comment

Use ordered map for recordparams, genargs,modarhs, etc...

https://github.com/Tessil/ordered-map This is a header only implementation

Add test for verilog generation with Generators having Types and Modules and Json as parameters.

Add ability to dump signals to a VCD file using the CoreIR simulator

Initially, we just need support for dumping the IO of the top level module to a VCD format. https://en.wikipedia.org/wiki/Value_change_dump

include verilog verification in testing infrastructure

This will depend on #668 since it includes the verilog gold file checking. In addition I want to add the following: - [ ] lint check using verilator for a...

Add argument passing mechanism to coreir binary for specific passes.

remove commonlib dependency on coreir binary

Replace include guards with #pragma once