Ross Daly

Fault silently allows poking non-existing ports

2

I would expect the following code to raise an error or warning trying to poke a bad port. When you try to peek a bad port, it does error. ```...

Creating a tester fails when the circuit is defined using circuit.sequential: The following code snippet fails complaining about a bad type for CLK ``` import magma as m from fault...

[Feature Request] Support for multiple clocks with different frequencies

2

It would be great to have fault generate the relative ordering between all the edges for multiple clocks. In terms of API, I think something along the lines of: ```...

Feature request: passing print statements through to verilator.

1

More debug features from python. One example is I would like to just stage a print statement. for example: ``` tester.print("SomeArbitraryString") tester.print(mysig1) ```

Feature Request: Access internal verilog values from fault

1

It would be very nice to do something along the lines of: ``` mymod_v = m.DefineFromVerilogFile("mymod.v")[0] tester = fault.Tester(mymod_v,mymod.clk) print(v_tester.peek(mymod_v.internal.)) ``` Most verilog simulators support something like this.

Similar to #484 the CLK and ASYNCRESET ports are always added to stateless classes with circuit.sequential. This causes issues when using verilator complaining about unused signals.

circuit.sequential fails on calls within branches

2

``` @m.circuit.sequential class A: def __call__(self, i: m.Bit) -> m.Bit: return i #Works @m.circuit.sequential class B0: def __init__(self): self.a0: A = A() self.a1: A = A() def __call__(self, i :...

It would be great if the following worked in magma ``` def gen_A(width): Data = m.Bits[width] @m.circuit.sequential class A: def __init__(self, rega_init: m.Bit, regb_init: Data): self.rega: m.Bit = rega_init self.regb:...

Tests an issue found with passing in the env. depends on fix provided by https://github.com/leonardt/ast_tools/pull/23

``` /Users/ross/dev/coreir/build/tests/gtest/googletest-src/googletest/src/gtest.cc:4082:33: error: implicit conversion changes signedness: 'const char' to 'unsigned char' [-Werror,-Wsign-conversion] if (IsValidXmlCharacter(ch)) { ~~~~~~~~~~~~~~~~~~~ ^~ /Users/ross/dev/coreir/build/tests/gtest/googletest-src/googletest/src/gtest.cc:4083:56: error: implicit conversion changes signedness: 'const char' to 'unsigned char' [-Werror,-Wsign-conversion]...