Update RAM generator to have a read latency parameter

[rdaly525]

[rdaly525]

@leonardt, I am in the process of adding a read latency parameter to the memory.ram generator. The default implementation will use a coreir.mem along with coreir.reg for read delay. Would it be possible to add a similar parameter to the mantle memory generator and have it use CoreIR's memory.ram?

This is needed to be able to have yosys infer BRAMS from verilog code (pointed out by @splhack)