Rakesh Moolacheri

modified bram_map, bram_final_map & cells_sim files to add fifo macros

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Signed-off-by: rakeshm Added fifo macros, modified bram_map.v, bram_final_map.v & cells_sim.v files.

Yosys flow is removing the gclkbuff instantiated in the design. Attached the design files and top.eblif file. [counter24_top.zip](https://github.com/SymbiFlow/yosys/files/4753167/counter24_top.zip)

Branch: Quicklogic : Functional issue in the design with Yosys generated edf

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## Steps to reproduce the issue 1. Run the attached design through Yosys flow - works fine 2. Run PNR of the EDF file created by Yosys on SpDE -...

Branch : Quicklogic : symbiflow supports only 32 IO's though device has 46 IO's

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Symbiflow supports only 32 IO's though device has 46 IO's Symbiflow throws error when a design has more than 32 IOs: Error 1: Type: Other File: /tmp/really-really-really-really-really-really-really-really-really-really-really-really-really-long-path/conda/conda-bld/vtr_1583635602183/work/vpr/src/pack/pack.cpp Line: 180 Message:...