Lucian Petrica
Lucian Petrica
Xilinx HLS IP can be free-running (they self-restart) for example by setting control mode to `ap_ctrl_none` in Vivado/Vitis HLS. This is a relatively common design pattern. I've added an additional...
This PR has two changes: - added bytesReceived and endOfPacket fields to hlslib::axi::Status which are set by datamovers when Indeterminate BTT mode is set - added constructors and casting functions...
This PR addresses #174 I added the following features: - two node attributes, `ip_cache_key` to store a key in an IP cache and 'disable_ip_synth' to instruct HLSSynthIP to skip a...
When stitching, the BD global clock/reset input ports are produced by making external the clock/reset of the first IP in the dataflow. The stitching logic assumed that the name of...
When debugging new FINN code it's helpful to get a debugger console and walk through the code. ATM the dataflow builder prevents this by redirecting debugger output to the log....
* PYNQ version (e.g. v2.6): 2.7.1 * Board name (e.g. Pynq-Z2): Alveo U280 * Description: ip_dict is incorrect when multiple memory banks are attached to one kernel AXIMM interface, e.g....
* PYNQ version: 2.7 * Board name: Alveo U280 * XRT version: 2.13.399 * Description: When getting a handle to a CU with 64b unsigned int arguments, pynq fails with...
* PYNQ version: 2.7.0 (pip installed) * Board name: Alveo (any) * Description: XRT version identification fails with newer XRT versions. This is because xrt_device.py at line 88 tries to...
Currently it doesnt seem like PyVerilator supports providing explicit lists of Verilog files to pass down to Verilator, or setting the top module explicitly. Verilator will only find the files...
I've implemented a systemc model enabling the CMAC to run in hardware emulation in conjunction with external software that emulates a switch. I've added an example application. PR is draft...