Fixed input clock/reset port name inference during stitching

[quetric]

When stitching, the BD global clock/reset input ports are produced by making external the clock/reset of the first IP in the dataflow. The stitching logic assumed that the name of those clock/reset signals on the first ip is ap_clk/ap_rst_n and if this is not the case, the stitching fails.

The fix utilizes the known port names to infer the correct BD global clock/reset names after making the ports external.