Yao Jing Quek comments

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                                            Yao Jing Quek

Create a utility that can convert SystemVerilog modules into ROHD

Some other references: https://github.com/Nic30/hdlConvertor/tree/master https://github.com/Nic30/hdlConvertorAst https://github.com/MikePopoloski/slang

Make `Logic`'s `toString()` method more insightful

@mkorbel1 Let me try to look into this.

Make `Logic`'s `toString()` method more insightful

- Adding Hierarchy - Showing the current value of the signals

Make `Logic`'s `toString()` method more insightful

- Logic's Name - Width

Replace generic `Exception`s with more specific or ROHD-related exceptions

Hi Max, I will pick up this issue as well.

chore(devtool): build devtool artifact and commit to other branch

> Were you able to get the extension running by pointing at the `artifacts` branch? > > I tried adding this into a `pubspec.yaml` (not in the `rohd` package itself):...

Add example on how to use Logic Array assignment would be good

https://gist.github.com/quekyj/5b6ec50f9bd95fce13f8ab8fed4dc453. Park here as reference.