Yao Jing Quek

Enable running the website repository in Github codespaces

4

### Describe the problem Error encountered when try to open with Github codespaces. Below are the creation logs: Open to review log ``` ================================================================================= 2023-07-14 06:18:42.137Z: Configuration starting... 2023-07-14 06:18:42.175Z:...

### Motivation An implementation of the code navigation through Flutter UI. It's helpful to the develop to track which signals in the code is causing the issue. ### Desired solution...

### Motivation We need a mechanism to search for the driver of a signal. ### Desired solution When a user perform an [event] in the UI, it will show which...

### Motivation The current codebase of the flutter UI is tightly coupled together lead to difficulty in writing test. ### Desired solution Refractor the riverpod state management to BLOC state...

### Motivation The experience of using the hierarchy viewer is not seamless. The signal updating is not auto, user need to manually click on the refresh button and click again...

chore(devtool): build devtool artifact and commit to other branch

3

## Description & Motivation To test out the unreleased version of the devtool_extension, we can allow github action to commit the build artifact and modified the .gitignore. So, user can...

## Description & Motivation Add vscode rohd snippet for auto-completion feature in vscode. Users now can install ROHD vscode extension and then use the auto-completion feature to write code. ##...

### Describe the bug During simulation, the function `WaveDumper` need to be place before any of the `Simulator` class else its going to throw the bug as shown below: ...

Add example on how to use Logic Array assignment would be good

2

### Motivation Add a simple example to website https://intel.github.io/rohd-website/docs/logic-arrays/ on how to use array assignment, users are confuse with: ```dart logicArray.elements[0]; // a[0] ``` Probably, example of assignment in conditionals...

A helper function to save generated System Verilog string as a file

1

### Motivation I'm wondering if we can have a helper function to save system Verilog module `generateSynth()` to a file. Its a pain to keep copy pasting the code below...