priyanka617
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priyanka617
hello, while trying to simulate the code on Xilinx Vivado, I'm getting no output at the o_fir_data_tb pin, and the input is latched to 16'h7FFF, please help me out here...
priyanka617
hello, while trying to simulate the code on Xilinx Vivado, I'm getting no output at the o_fir_data_tb pin, and the input is latched to 16'h7FFF, please help me out here...