Dan

unexpected behavior against multiple conflicting drivers in odin BLIFReader with yosys elaborator

5

When using yosys+odin with the 'paj_boundtop_hierarchy_no_mem' verilog input file, with or without arch file, everything looks fine and the verilog file is being elaborated and partial mapped successfuly, however if...

Parmys (Partial Mapper for Yosys) plugin

2

This PR provides _Parmys_ (Partial Mapper for Yosys) plugin which performs intelligent partial mapping (inference, binding, and hard/soft logic trade-offs) from [Odin-II](https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/ODIN_II).