Dan

Thanks @sdamghan for the reply, in the verilog file there is an issue, > **paj_boundtop_hierarchy_no_mem.v:225** `boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10,...

Thanks, as we discussed, for example for the `boundtop` benchmark the number of input nodes are different in the stats for ODIN-II vs Yosys+ODIN-II, but the number of inputs in...

I just tested `stereovision0.v` on `simple-7series.xml` and it was OK. The command history: ``` 504 git clone https://github.com/verilog-to-routing/vtr-verilog-to-routing.git vtr 505 cd vtr 506 make -j10 507 cd vtr_flow/scripts/ 508 ./run_vtr_flow.py...

@alirezazd we can have one of the students (Navid or Ritwik) working on the `temp_dir` issue.

@vaughnbetz Regarding the `git submodule` issue, I think this is some flaky behaviour related to the infrastructure and perhaps networking issues, since everything is green in the scheduled task at...

The warnings are related to `shift/reduce conflicts` within the `verilog_bison.y` file and have to be inspected separately. @alirezazd

@alirezazd @duck2 I believe this is not related to `Parmys` itself and `Yosys` is throwing the exception---before `Parmys`. So, whether `Yosys` has an issue or the input circuits should be...

@kgugala once the tests are passed, this PR is ready to be reviewed/merged.

When using `litex-hub::vtr` package as VTR dependency, the ci gets the following error while performing linking to the vtr binaries: ``` lto1: fatal error: bytecode stream in file ‘/home/runner/work/yosys-f4pga-plugins/yosys-f4pga-plugins/env/conda/envs/yosys-plugins/lib/libarchfpga.a’ generated...