Paul Swirhun

Extensibility guidance - customizing build flags for various embedded platforms

4

This is not a bug, but rather a request for information and/or documentation for your project. I'm a big fan, by the way, and the use of the long awaited...

Directories are not copied in export() function

4

I found that only directories (empty, with none of the expected contents) are copied, due to what I think is a bug in `capi2/core.py`: https://github.com/olofk/fusesoc/blob/584d0aeb7d99105eb2dfb1d7003cd0e27aad13c6/fusesoc/capi2/core.py#L121 From lines 108 to 125...

This is my first time using cocotb-test and I'm using it with Verilator. I have used Verilator fairly extensively with just C++ testbenches. I'm following some alexforencich examples for cocotb-test...

ip_64 flushes one payload transfer too many after ARP cache miss

2

I haven't simulated this; I have just been looking at your code to see if verilog-ethernet could be a compatible replacement for a similar, lesser version that I wrote and...

SV interface name collision in different parts of design hierarchy -- Verilator muddles names between levels of hierarchy

7

When I have an array of SV interfaces like this, Verilator works as expected for N=4. ``` AXIS_IF.master m_axis_if[N-1:0] ``` However, when I change to N=1, I get errors where...

Verible formatter fails when third line of port list is blank

1

v0.0-3454-g7fdc2876 Commit 2023-12-20 Built 2023-12-20T15:18:36Z **Test case** ```systemverilog module my_module ( input logic clk_pl_100 // a comment , input logic aresetn // another comment , output a , output b...

In an addrmap with some external memories followed by some registers, peakRDL-regblock only generates the registers if they are "loose" members of the addrmap scope. If the registeres are nested...

For this counter description: ``` signal { sync; activehigh; } latch_stats; reg stats_cnt_reg_varincr #( string regdesc = "", string fielddesc = "", longint regwidth = 32, longint fieldwidth = 32,...

There was some discussion of backdoor access in other threads, but at peakrdl-uvm==2.3.0, I don't see it doing what I would expect in the generated UVM file. I'm a design...