optimsoc
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optimsoc
OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
We get a lot of warnings like the following during synthesis ~~~ WARNING: [Synth 8-2898] ignoring assertion [/data/home/no56hud/src/optimsoc/objdir/examples/fpga/nexys4ddr/system_2x2_cccc/build/optimsoc_examples_system_2x2_cccc_nexys4ddr_0/src/wallento_svchannels_nasti_0/rtl/verilog/nasti_channel.sv:46] ~~~ These warnings only clutter output and don't help anything, can we...
Currently we have one `optimsoc::config_t` data structure which we pass as `CONFIG` parameter to most modules. With the development of the host tile (#36) and the ethernet tile (#91), we...
Currently, we have a couple of purely structural Verilog files in OpTiMSoC: the toplevel files at various levels of the hierarchy. Creating these files is tedious and error-prone (getting wiring...
WIP pull request for issue #90 To test out the changes, first build optimsoc using ```sh cd ~/src/optimsoc ./tools/build.py --without-examples-fpga --without-examples-sim --link-hw --without-docs ``` Then build the example project using...
Goal is a compute_tile_dm system with a Ethernet MAC attached to the tile-internal Wishbone bus. This ticket is about the hardware implementation only. (The software implementation is developed in lockstep...
@ppenna already started modeling the OpTiMSoC network adapter in QEMU to help with the development of the NoC driver. The initial code is available at https://github.com/ppenna/qemu. After finishing bringup of...
**Brief** The current implementaiton of the NoC driver only alllows one process at a time to use an endpoint. Ideally, however, would be to have the acess to a endpoint...
**Description** When running the 2x2 singlecore system example and forcing core 0 of tile 0 to send data to itself, the execution hangs. This problem is likely to be caused...
The WIP Linux NoC driver implementation lives in optimsoc/linux currently. Once it's finished and passed internal review, submit upstream to get a full review there.
