Disable reporting of "ignoring assertion" warnings in Vivado

Open imphil opened this issue 7 years ago • 0 comments

We get a lot of warnings like the following during synthesis

WARNING: [Synth 8-2898] ignoring assertion [/data/home/no56hud/src/optimsoc/objdir/examples/fpga/nexys4ddr/system_2x2_cccc/build/optimsoc_examples_system_2x2_cccc_nexys4ddr_0/src/wallento_svchannels_nasti_0/rtl/verilog/nasti_channel.sv:46]

These warnings only clutter output and don't help anything, can we suppress them with a vivado argument?

Jan 27 '18 14:01 imphil