optimsoc
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OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
The NoC primitives are missing cocotb tests. Old code by @wallento is available at https://github.com/imphil/optimsoc/commit/32162b1b9bf276de0d969f7e0c64b4856a0886b5 and can potentially be used as starting point.
Add a clock domain crossing at the NoC interface.
Currently in the OpTiMSoC source code, additional hardware such as bootrom, and data/inst. cache have been disabled. Is there any plan to include this functionality or would the design work...
It seems that objcopy has a "verilog" target option which creates vmem files. See if that option works for us and remove bin2vmem in this case.
The idea is that we have one compute tile that runs Linux and has a UART interface or similar to the outside world.
Our example design `compute_tile_sim` currently fails the Verilator lint. Some lint warnings seem to be bogus, but are hiding the important ones. 1. Find a way to suppress the warnings...
Eclipse is a rather nice choice for working on OpTiMSoC as it is able to support different languages through plugins with advanced features like auto-complete and syntax checking. However, currently...
When sending a message in which one data item is a negative number the `optimsoc_mp_msg_recv()` function never returns. Sending a message with a positive number in it is received. The...
Currently MAM is inserted into the memory path in a rather "hackish" way. We should make the MAM a normal master on the bus. @wallento I think you already have...