cva5
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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
Respected sir I trust this email finds you well. My name is Tanishq.S, and I am a student from PES University, India. I am reaching out along with my team...
Respected sir Subject: Request for Assistance - CVA-5 Processor Simulation I trust this email finds you well. My name is Tanishq.S, and I am a student from PES University, India....
In my fork, I have added some functionality to CVA5. I have a significantly modified environment in which I test, so cannot simply issue pull-requests right now. Is there interest...
When an interrupt, such as a timer interrupt occurs, the captured MEPC does not always reflect the correct address where to continue execution after the interrupt finishes. This can randomly...
The documentation says the RISC-V A-extension for atomic instructions is supported, but now that I am attempting to use it, it seems broken. How tested / working is the AMO...
Hi, I doing some project with this core on Zedboard but got some problem with the provided Hardware Setup from the Taiga Wiki page. When I run the bitstream down...
hi, i'd like to use the fpga jtag prot to debug this core, and i see the jtag-related modules inside of the code,. Is there any example project to demo...
Hi, Thanks for your efforts. I tried to run through the following path test_benchs/cva5_tb.sv, after creating a questasim makefile. But, I found out a lot of x propagations that failed...
Hello, In your old version of Taiga, you didn't mention at your paper of Taiga configuration ........ a specific type of your cache architecture. I have found that it is...
Hello, We are working on integrating two cores of your processor into one multiprocessor system. We have some questions. Is your core include caches that are write-through or write-back?
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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.