Cache architecture of the CVA5 processor?

[Mohamed1984]

Hello,

We are working on integrating two cores of your processor into one multiprocessor system.

We have some questions.

Is your core include caches that are write-through or write-back?

[e-matthews]

The data cache is write-through. For multi-core coherency support, it has support for external invalidations if the config option: USE_EXTERNAL_INVALIDATIONS is enabled for the data cache. The interface for which (l1_arbiter_return_interface) is defined in: external_intervaces.sv

[Mohamed1984]

Thank you for your response

On Thu, Mar 9, 2023 at 10:09 PM Eric Matthews @.***> wrote:

The data cache is write-through. For multi-core coherency support, it has support for external invalidations if the config option: USE_EXTERNAL_INVALIDATIONS is enabled for the data cache. The interface for which (l1_arbiter_return_interface) is defined in: external_intervaces.sv

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[MikeOpenHWGroup]

Hi @Mohamed1984. Does this answer your question? If so, please close the issue. Thanks!