core-v-mcu
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This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
I get the following error when I run 'make all-vivado' command in Vivado version 2022.2 without any changes made. ``` Time resolution is 1 ps run -all core_v_mcu_tb.qspi.mem_access @ 0...
### Is there an existing core-v-mcu bug for this? - [X] I have searched the existing bug issues ### Bug Description I attempted to run the application on the Genesys2...
### Is there an existing core-v-mcu bug for this? - [X] I have searched the existing bug issues ### Bug Description To do simulation using verilator and gtkwave we are...
### Is there an existing core-v-mcu bug for this? - [X] I have searched the existing bug issues ### Bug Description In the `rtl/includes/pulp_soc_defines.svh` file [here](https://github.com/openhwgroup/core-v-mcu/blob/master/rtl/includes/pulp_soc_defines.svh#L142) I see the following:...
### Bug Description In the [apb_gpio](https://github.com/openhwgroup/core-v-mcu/blob/31af0754398729278e3bdf628294a46324ad4253/rtl/apb_gpio/rtl/apb_gpio.sv#L102) module of CORE-V-MCU we have a couple of code blocks that are similar to the code snipit below. This implements a combinatorial loop on...
### Task Description Currently the micro-DMA chapter of the User Manual is a description of how the uDMA works. We need a programmer's view that explains how to write/read the...
Update to the uDMA UART chapter to define the term `volatile CSR` and indicate which of the UART CSRs are volatile.
A (mostly empty) shell of the APB Advanced Timer peripheral exists at `docs/doc-src/ip-blocks/apb_adv_timer.rst`. This chapter needs to be updated such that the Reader understands _what_ the peripheral does, a high-level...
### Task Description Update the [Micro-DMA Subsystem](https://docs.openhwgroup.org/projects/core-v-mcu/doc-src/udma_subsystem.html) chapter of the User Manual to explain selects of the various uDMA peripherals. ### Description of Done Accepted pull-request. ### Associated PRs _No...