core-v-mcu

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Verilator model does not work

1

With the latest master branch (commit 53a5d08) , the Verilator model library builds but will not run, giving the following error: ``` $ ./testbench.exe Timescale 1ns / 1ns TOP.core_v_mcu.i_soc_domain.l2_ram_i.bank_sram_pri0_i.u0 %Error:...

jeremybennett

CI/CD Bring-up

12

Install continuous delivery of FPGA bitstreams for: - Genesys 2 - Nexys A7 I've already set-up the required FPGA container. The remaining challenges are: - [ ] Make sure PULPissimo...

zarubaf

UDMA module for sdio doesn't wait the correct amount of time for block write to complete. The IP in sdio_txrx_data only waits 512 baud rate clocks for a block write...

gmartin102

Centralize compiler macros in a top-level package

3

There is at least one instance of a compiler macro in CORE-V-MCU that is defined and used in disjointed parts of the RTL. The macro in question is `USE_FPU`. It...

MikeOpenHWGroup

944 warnings raised by Verilator

9

We build the Verilator model as follows: ``` fusesoc --cores-root . run --target=lint --setup --build openhwgroup.org:systems:core-v-mcu ``` Verilator raises 944 warnings. The warnings and frequency counts are: ``` ALWCOMBORDER 1...

jeremybennett

Remove `xilinx_interleaved_ram` and `xilinx_private_ram`

1

Block RAMs can be inferred using either the correct coding style or Xilinx Parameterized Macros (XPM) such as used in the `tc_sram`s.

zarubaf

Re-think FPGA specific modules

1

Currently the FPGA and ASIC specific modules are `ifdefed` and scattered throughout the code. I would propose two fixes to that: - SRAMs are wrapped in technology unspecific ways. During...

zarubaf

Remove global header files from IPs

1

Searching all IP repositories for `pulp_soc_defines.sv` (`rg -w pulp_soc_defines -g '!core-v-mcu/*'`) leads to: ``` cluster_interconnect/rtl/peripheral_interco/AddressDecoder_PE_Req.sv 46:`include "pulp_soc_defines.sv" ``` IPs should be stand-alone and should not depend on includes. Let's refactor...

zarubaf

Fix Genesys2 FPGA builds

2

Due to the IO changes, there isn't a valid IO assignment for the Gensys2 board available. If that has been fixed we can try to re-enable the FPGA target.

zarubaf

CORE-V MCU Bring-up

3

Legacy, but the sub-tasks hold. > Migrate Content from `master`: > > - Instantiate CV32E40P. A fork of the SoC is going to be necessary. > - Update documentation. >...

zarubaf