core-v-mcu
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openhwgroup
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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In case of PR review approved by an OHW member (specifically: Florian or Mike or Davide) the core-v-mcu CodeBuild job is started
Registers are accessed via abstract commands using the following mapping. | Address range | Registers | |-----------------|--------------------------------------------------------| | 0x0000 - 0x0fff | CSRs | | 0x1000 - 0x101f | GPRs...
Hi @davideschiavone, what is the [src_files.yml](https://github.com/openhwgroup/core-v-mcu/blob/master/rtl/core-v-mcu/src_files.yml) used for?
Hi, I was wondering if there are any plans for other FPGA ports. I'd mostly be interested in Zedboard and ZCU102. In the past these ports (and softcores as standalone...
Hello! Can the EFPGA module of your project support all circuits? There is a question about how to realize the reconfiguration of any circuit after your chip is taped out....
Add a readme/howto on creating mem init files for simulation. Include any custom scripts to convert from SREC to required formate for various simulators
The verilator model under development for the CORE-V MCU has been used to access the FPU registers. It appears that register `f0`, which should be one of eight temporaries is...
Following file: https://github.com/openhwgroup/core-v-mcu/blob/master/rtl/core-v-mcu/top/core_v_mcu.sv contains illegal assign statements (lines 485, 486): assign s_test_mode = '0; assign s_dft_cg_enable = '0; because variables s_test_mode and s_dft_cg_enable are also driven by output ports of...
The CORE-V-MCU instantiates the "fpnew" floating point IP from the pulp-platform team. As discussed in #189, the CV32E40P does not make use of this floating point unit, so it really...
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This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.