openwifi-hw
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open-sdr
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
I added support of sdrpi for this branch , try pull request fro sdrpi hw,I will modify it if any error. I walked through all steps in readme.md and everything...
May I ask which licenses Vivado needs besides Xilinx Viterbi Decoder license, because the Bitstream and HDF files we often compile cannot be used, thank you
Hello, I am currently trying to extract the samples after the CFO correction out of Verilog to the processor and to print them to a console or similar. I am...
I think it should be possible to get openwifi running on plutosdr, if the sidechannel could be disabled with a parameter. I already found some places where ressource usage could...
Hello, Dr. Jiao. We are using your image. **My modification** I saw that the top file for **side_ch** had a predefined data bit width and thought I could modify it...
Hi I am simulation the openwifi fpga code in vivado and need little info about data structure of test vector Stored in tx-intrf.mem file and other two file also. How...
First of all, I want to congratulate you on your work on this project, which is a valuable contribution to the community. However, during my investigations, I have encountered some...
Hi jiao, thank you for your project. I'm trying to simulate the openofdm_tx , openofdm_rx and some interface IP simultaneously. I don't know much about 802.11. I'm trying to modify...
hello sir, thank you for your amazing work.I would like to ask you some tips about the module “sync_short”. There is a output named “phase_offset”,Is this the frequency offset you...
`assign enc_reset = phy_tx_arest | state1 == S1_WAIT_PKT | plcp_bit_cnt == 23 | plcp_bit_cnt == 47;` 您原来的代码中，会在SIG字段的第23bit和第47bit对BCC模块进行reset。当发送ht帧时，这个机制会导致在SIG字段中重置BCC模块，与接收机的解码机制是不是有一定区别。接收机中好像时直接把所有数据直接一起解码的，不会区分不同symbol。
