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Results 324 unified-runtime issues
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This PR: * Refactor the platform and device fixtures to be included in smaller files. * Remove duplicated code in initializing platform environment and initializing platform fixtures.

conformance

The dependabot.yml configuration is required by Scorecard. For now, PR adds a simple dependabot version and hashes update (open PR if new version is available). In the future, the configuration...

ci/cd

The Level Zero USM allocation functions are returning non-null pointer values when the alignment is not a power of two which contradicts the spec requirements. This PR fixes that. For...

level-zero
ready to merge

This matches the previous design in PI, which is better suited for handling underlying native types that aren't pointers (e.g. CUdevice in CUDA). LLVM PR: https://github.com/intel/llvm/pull/13705

common
conformance
level-zero
cuda
hip

Until now we've had multiple styles throught the project. This doesn't buy us anything for contributors as each source file might be different - totally negating the point of having...

loader
common
conformance
level-zero
cuda
hip
native-cpu
sanitizer

Adding more validation for making sure that the sampler was applied in a right way inside the adapter implementation for `urKernelSetArgSampler` entry. Since we cannot guarantee the results between adapters,...

conformance

Also make returns for this consistent across adapter implementations (i.e. actual IL if that's supported, otherwise return UNSUPPORTED_ENUMERATION). resolves #1138 LLVM testing https://github.com/intel/llvm/pull/12265

conformance
specification
level-zero
cuda
hip
opencl
native-cpu

LLVM testing https://github.com/intel/llvm/pull/12269

loader
conformance
specification
level-zero
cuda
hip
opencl
native-cpu

This is a batch PR containing a number of spec-motivated refactors/small changes. Changes include: * #1118 * #1082 * #1125 * #1145 * #1215 * #1136 llvm testing https://github.com/intel/llvm/pull/12681

loader
conformance
specification
level-zero
cuda
hip
opencl
native-cpu
command-buffer

DPCPP changes: - https://github.com/intel/llvm/pull/12938 (enables `sycl::memory_order::seq_cst` in `sycl::atomic_ref`)

hip