Olof Kindgren

Wow, I'm slow. But I think I finally understand. And if I did understand, I think it will still be much easier to handle cache invalidation by the generator itself....

As a first step, I believe we need to allow the generators to have more control over their data. IIRC, today FuseSoC clears out the data dir before calling the...

One common use for this would be to set `errors: ["!tool_verilator? (Testbench only supports Verilator)"]` It could also be used to check for invalid combinations of use flags `errors: ["!spi?...

Hmm... I didn't think about targets without toplevels. Maybe it's easiest to drop this idea and go start looking at adding variables to core files, so we can have e.g....

This looks surprisingly clean, which is encouraging. Does it still work with the `pos` argument for generators? I think I understand how the new resolving works, but 'm not 100%...

FTR, I'm using position in several cases. One example is SweRV where a script is generating the CPU configuration, which must be added before the core. Note, this uses `first`...

Good catch. I just checked and the rest of them looks correct. Tests would be good though

Hi @benreynwar I had totally missed this one. Just writing to know that I've seen it now. Unfortunately I have only taken the time for a quick look and not...

Haha. Before seeing your latest comment, I just started reading through it thinking it all looked very complicated and that it would need to take time to wrap my head...

My ideas so far: For the first case, create a generator that converts (n)migen cores to verilog and allows them to be used in a verilog flow. This would a)...