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MnAnalyzer

Task rejected, since ADPCM was reversed from another place.

But the lower 2 mux looks like malformed to me. There is one more wire missing. Either that or I missed it. ![image](https://user-images.githubusercontent.com/5828819/162498743-2f8b059b-8575-47ce-9563-da5796b078c1.png)

APU Tran Issues from ttlworks

![image](https://user-images.githubusercontent.com/5828819/181719398-672ec632-9079-4a0b-8fcb-09708a7916b1.png)

APU Tran Issues from ttlworks

![image](https://user-images.githubusercontent.com/5828819/181719480-64ab0002-a1bb-4307-ad38-30fc61a17902.png) ![image](https://user-images.githubusercontent.com/5828819/181719520-c805a2bd-50d3-401a-8aae-cb6026e4b1c8.png)

APU Tran Issues from ttlworks

![image](https://user-images.githubusercontent.com/5828819/181719594-abcbfe3d-932b-45e9-ac7a-56d11683c42c.png) EDIT: /ACLK4

APU Tran Issues from ttlworks

![image](https://user-images.githubusercontent.com/5828819/181719668-861194f8-9a53-40e1-b35a-c573ac362e67.png) I don't see the problem, I've checked the topology and the transes 50 times. EDIT: Actually... hehe ![image](https://user-images.githubusercontent.com/5828819/209552322-31d42d0f-d9af-4800-a3be-199755d035dd.png)

APU Tran Issues from ttlworks

APU > DPCM > frequency counter LFSR > order of Bits Considering the [wikipedia page](https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Example_polynomials_for_maximal_LFSRs) about LFSRs, for the [DPCM frequency counter LFSR](https://github.com/emu-russia/breaks/blob/master/BreakingNESWiki/imgstore/apu/dpcm_freq_counter_lfsr_tran.jpg) the naming order of Bits is swapped....

APU Tran Issues from ttlworks

APU has a frequency LFSR in the DPCM section, and a frequency LFSR in the Noise section. Control signals for both LFSRs are labeled FLOAD,FSTEP in your schematics. That might...

Old APU Test Pattern

See also here: https://www.nesdev.org/wiki/RP2A03_Programmable_Interval_Timer (Research by nesdev guys)