LTG

Vending_Machine

1

**Describe the bug** `I don't know huhu ` **The code** `module vending_machine( input clk, input nickle, dime, quarter, output reg soda, output reg [3:0] change ); //parameter for state assignment...

Why my code doesn't produce a FSM ?

2

**Describe the bug** TerosHDL cannot produce a FSM **Code** ` `timescale 1ns/1ns module vending_machine( input wire clk, input wire rst_n, input wire nickle, input wire dime, input wire quarter, output...

Failed to access library 'C:\Users\namhe\.teroshdl_fryIl_' at "C:\Users\namhe\.teroshdl_fryIl_".TerosHDL: modelsim(vlog-19)

4

It's look like there is some errors.  Here is the folder:  Maybe my C:\Users\namhe is lacking the ".teroshdl_fryIl_". How can I fix that ?

**Describe the bug** I tried to generate FSMs from the this source code (https://github.com/open-logic/open-logic/blob/main/doc/axi/olo_axi_master_simple.md) **To Reproduce** Code to reproduce the error. **Code** Code to reproduce the error. **Please complete the...