vscode-terosHDL
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Vending_Machine
Describe the bug
I don't know huhu
The code
`module vending_machine(
input clk,
input nickle, dime, quarter,
output reg soda,
output reg [3:0] change
);
//parameter for state assignment
parameter S0 = 4'd0, //soda = 0, change = 0
S5 = 4'd1, //soda = 0, change = 0
S10 = 4'd2, //soda = 0, change = 0
S15 = 4'd3, //soda = 0, change = 0
S20 = 4'd4, //soda = 1, change = 0
S25 = 4'd5, //soda = 1, change = 5
S30 = 4'd6, //soda = 1, change = 10
S35 = 4'd7, //soda = 1, change = 15
S40 = 4'd8; //soda = 1, change = 20
//parameter for the change
parameter C0 = 3'b000, //change = 0
C5 = 3'b001, //change = 5
C10 = 3'b010, //change = 10
C15 = 3'b011, //change = 15
C20 = 3'b100; //change = 20
reg [3:0] state, next_state;
//input equation (ref: state diagram)
always @(*) begin
case (state)
S0: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S0;
endcase
S5: case({nickle, dime, quarter})
3'b100: next_state = S10;
3'b010: next_state = S15;
3'b001: next_state = S30;
default: next_state = S5;
endcase
S10: case({nickle, dime, quarter})
3'b100: next_state = S15;
3'b010: next_state = S20;
3'b001: next_state = S35;
default: next_state = S10;
endcase
S15: case({nickle, dime, quarter})
3'b100: next_state = S20;
3'b010: next_state = S25;
3'b001: next_state = S40;
default: next_state = S15;
endcase
S20: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S20;
endcase
S25: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S25;
endcase
S30: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S30;
endcase
S35: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S35;
endcase
S40: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S40;
endcase
default: next_state = state;
endcase
end
//Seq logic
always @(posedge clk) begin
state <= next_state;
end
//output equation
always @(*) begin
case(state)
S0: begin soda = 0; change = C0; end
S5: begin soda = 0; change = C0; end
S10: begin soda = 0; change = C0; end
S15: begin soda = 0; change = C0; end
S20: begin soda = 1; change = C0; end
S25: begin soda = 1; change = C5; end
S30: begin soda = 1; change = C10; end
S35: begin soda = 1; change = 15; end
S40: begin soda = 1; change = 20; end
default: begin soda = 0; change = C0; end
endcase
end
endmodule `
what is the issue with your code ?