nachiket
nachiket
For FPGA execution of OpenCL kernels, the board expects 64-byte aligned host arrays. However, there seems to be no way to get numpy arrays to obey custom alignments (It seems...
In VTR SDC syntax, how do I disable timing analysis from input/output ports to the LUTs? I only want to do analysis on internal LUT-LUT paths. I checked set_false_path and...
When running remotely from a server from a Mac host, the VTR GUI window size exceeds screen height. The resize option and a few buttons happen to go below the...
I'm not sure I fully understand phase option in the drawing tool. Sorry, if this is covered in a document somewhere, but I'm only operating off the tutorial. Here's an...
Hi -- I'm trying to get `gcc-python-plugin` to work on MacOSX. I am facing the following issues with `gcc-8` ``` gcc-8 -I/usr/local/Cellar/gcc@8/8.3.0_2/lib/gcc/8/gcc/x86_64-apple-darwin19/8.3.0/plugin/include -I/usr/local/Cellar/gcc@8/8.3.0_2/lib/gcc/8/gcc/x86_64-apple-darwin19/8.3.0/plugin/include/c-family -I. -I/usr/local/include -O2 -Werror -g -fPIC -fno-strict-aliasing...
--- name: Pull request about: Push a change to this project --- ### Motivate of the pull request - [x] To address an existing issue. If so, please provide a...
Right now I see VPR arch files in the `$OPENFPGA_ROOT/openfpga_flow/vpr_arch` folders being used in the `task.conf` file reference via `${PATH:OPENFPGA_PATH}` variable. How might I be able to supply my own...
Is it currently possible to use the int8 type for training and inference with nanoGPT? I only see different floating-point options in train.py. What might it take to add such...
I'm trying to generate an FPGA with different tiling configurations i.e. 2x2, 4x4, 8x8, etc. I see there are two places to edit the VPR size 1. task.conf `openfpga_vpr_device_layout=8x8` 2....
SDC files generated by OpenFPGA have buggy Verilog module hierarchy paths. I had a makeshift script to fixup the paths but it seems to have gotten worse, unless I'm doing...