vtr-verilog-to-routing
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Published
20 hours ago •
verilog-to-routing
verilog-to-routing
Disable timing analysis for paths to/from IO pins
In VTR SDC syntax, how do I disable timing analysis from input/output ports to the LUTs? I only want to do analysis on internal LUT-LUT paths.
I checked set_false_path and set_disable_timing but it does not look like either would work for this?
