Norbert Kremeris

Tested and verified working correctly with the following args: --low-key C2 --high-key C7 --key-skip 6 --midi-port-name "CH345:CH345 MIDI 1 32:0" (using USB midi interface CH345) --audio-interface-index 17 (using jack/pipewire) --loop

RocketChip with L2 cache - works in litex sim, works on digilent nexys video with cpu-mem-width is 64, breaks with 128

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Hi All! I'm trying to integrate the L2 InclusiveCache from ChipsAlliance (https://github.com/chipsalliance/rocket-chip-inclusive-cache) with a single Rocket core to be used inside the Litex SoC. I can confirm that it boots...

Hi All, After updating to the latest docker image (docker pull ucbbar/chisel-bootcamp), running the setup cell on any of the pages no longer works due to a permission problem, as...