Matthew Wielgus
Matthew Wielgus
Thank you for the help. I replaced: ``` create_clock -name jtag_clock -period 15.000 $tck_pin ``` with: ``` set part_family [get_property FAMILY [get_parts $xilinx_part]] if { { $part_family eq "kintexuplus" }...
I am using a Waveshare Platform Cable USB II [Clone](https://www.waveshare.com/platform-cable-usb.htm). It has thus far worked well for me. No issues when JTAG programming 128MB of FPGA Configuration Memory or otherwise...
I fixed it and it turned out to be trivial. The Innova-2 Flex I am targeting controls JTAG access to prevent accidental Configuration Memory overwrite. I thought it was simply...
In case someone needs to debug their JTAG Adapter, interleaved `xsdb` and `hw_server` logging may be useful. `sudo gedit /tools/Xilinx/Vivado/2021.2/scripts/xsdb/xsdb/xsdb.tcl` and add the core JTAG-related logging options to the call...
It is possible to redirect `xsdb` output to both the screen and the log file but usage is messy. Lines are repeated or disappear. ```Shell (/tools/Xilinx/Vitis/2021.2/bin/unwrapped/lnx64.o/rlwrap -rc -f /tools/Xilinx/Vitis/2021.2/scripts/xsdb/xsdb/cmdlist /tools/Xilinx/Vitis/2021.2/bin/loader...
I'm not sure what you are trying to accomplish but I gave up on the [*dma_ip_drivers* XDMA `tests`](https://github.com/Xilinx/dma_ip_drivers/tree/master/XDMA/linux-kernel/tests). I believe they are meant for the [example design](https://docs.xilinx.com/r/en-US/pg195-pcie-dma/Available-Example-Designs) as it compiles...
The example designs are not easily altered. They exist to prove functionality. I strongly recommend you move on to an IP Integrator Block Diagram design. You can follow the [XDMA...
When you edit the Range (Memory Size) in the [Address Editor](https://docs.xilinx.com/r/en-US/ug994-vivado-ip-subsystems/Addressing-for-Block-Designs) and leave the Block Memory Generator on Auto that value (Address Width) will be propagated throughout the project. From...
The XDMA IP Block uses Block RAM for internal buffers, variables, etc. That reduces the available pool of BRAM Blocks.  When you generated your XDMA Example...
In the XDMA Example project, `xdma_app` connects XDMA `M_AXI` to the Block Memory `S_AXI`:  Vivado will not let you directly connect two busses with different data widths as...