Maciej Dudek

@enjoy-digital what do you think?

So it failed on picolibc, and not on this upconverter, it states that meson is not installed

@enjoy-digital could you take a look?

@tangxifan RR graph correctness is checked by running `check_rr_graph()` at the end of `build_rr_graph_fpga_interchange`. As far as I understand RR edges are CHANX/CHANY, site to CHANs connections. The main function...

Resently I had no time to work on it, but I'll get back to it.

Some time ago I tried using 64-bit wishbone with LiteSDCard, and as far as I remember It worked, but there is an issue here https://github.com/enjoy-digital/litex/blob/78c1751c4781ffe156128748810ee4af85fee058/litex/soc/interconnect/wishbone.py#L211 as `Interface()` is created in...

`ChannelQueue` is XLS IR class that is wraps channels, both single value and streaming. IRSingleValue, IRStream and IRAXStreamLike will use `ChannelQueue` to send/receive data from simulation. `AXIStream-like` uses `ChannelQueue` to...

I think this PR was to large to be done as a single unit. So it is now split into 4 PRs: - [ ] #1176 - [ ] #1177...

Closing this PR in the favour of the demonstrator repo.

@amykyta3 sorry for pinging you directly, but could you take a look?