Michael Singer
Michael Singer
On page 26, the full adders `EFYK` and `EJOK` should get `V6` and `V7` for their "A" inputs, not `D6` and `D7`. Btw. the the title of this page is...
On page 14, `FAPE` is actually a NAND gate, not an AND gate.
On page 25, the second input of OR gate `RUTE` should be driven by `RACU`, not `RACO`. Fixing that fixes the `MOE` output pin.
By simple I mean the output buffers that only have one connection. These are: * `SOUT` gets inverted by `KENA` on page 5. It must be inverted at the output...
`AWOD` is actually a NOR gate, not an OR gate. It generates the timing for the three chip select signals `CS`, `MCS` and `A15`.
As already pointed out in #56, the data of the OAM RAMs is inverted, so the labels `OAM_A_D0`-`OAM_A_D7` and `OAM_B_D0`-`OAM_B_D7` on pages 25, 28, 29 and 31 should have a...
Ok, #54 was just the beginning... I'm very sure all inputs of the chip are inverting. Let's go through them: * `RESET` is already correct. It represents the pad `!RST`....
In #11 I reported on the smaller tri-state buffers, but haven't figured out the bigger ones. Turned out that the bigger ones are all non-inverting. They pass the signal through...
The signals `T1` and `T2` that originate directly from their respective input pads should actually be marked as inverted. Just like the `RESET` signal is (but the other way around)....
On page 32, the DFF `MEGU` is one of those DFFs that only have a `Q` output. In the schematic though, the `!Q` output is connected. This is wrong. It...