Leo Moser

Simple interface throws warning, generates wrong code

3

First of all, thank you all for your great work! I tried to process a simple interface: ```SystemVerilog interface bus_if; logic out; modport master(output out); endinterface module bus_master (bus_if.master bus,...

Perhaps this is similar to #2053, but I wanted to report it anyway. When I tried to process this file, with the input of the interface assigned to its output...

This PR updates the DLL range in the Housekeeping SPI docs to match reality. I measured the following frequencies on my MPW-8 chips: | Chip | Measurements | | Calculated...

Inject custom Verilog into the flow

2

### Description Hello! While writing a custom step I'm facing the challenge to inject custom Verilog into the flow. By this I mean the ability to add new files to...

Failing CI

1

The CI has been failing on various LVS jobs for over a year now. Is this expected or is it a regression? And what can we do to fix it?

Update sky130_fd_pr to pull the change to the `spiceinit` file.

XSection is an additional package for KLayout that allows to generate cross sections. Compared to the 2.5d view it can model individual process steps. See here for more information: https://klayoutmatthias.github.io/xsection/...

Feature request: D25 setup for KLayout

2

KLayout has a built-in 2.5d view which allows you to view your circuit in semi-3d. See here for more information: https://www.klayout.de/doc/about/25d_view.html sky130 has a basic setup that could be used...

Relax metal filler rules

2

We have seen in the previous tapeouts that fill generation still proves to be a challenge. This may be partly due to the current fill generation scripts, which do not...

Metal1.filler in sealring

9

This commit added `Metal1.filler` under the `Passiv.drawing` of the sealring: https://github.com/IHP-GmbH/IHP-Open-PDK/commit/516b01c3a0f7a7a1d6e0dfe2875fceddd97c84e7 This is a violation of rule `M1Fil.a2`, as its side is much larger than 5um. @sergeiandreyev Do you remember...