Interface loopback throws warning, generates wrong code

[mole99]

Perhaps this is similar to #2053, but I wanted to report it anyway.

When I tried to process this file, with the input of the interface assigned to its output in bus_master:

interface bus_if;
    logic in;
    logic out;
    modport master(input in, output out);
endinterface

module bus_master (bus_if.master bus);
    assign bus.out = bus.in;
endmodule

module top (input logic din);
    bus_if bus();
    assign bus.in = din;
    bus_master m0(bus);
endmodule

I get three warnings:

Generating RTLIL representation for module `\top'.
/path/to/file.sv:13: Warning: Identifier `\bus.in' is implicitly declared.
Generating RTLIL representation for module `\bus_master'.
/path/to/file.sv:8: Warning: Identifier `\bus.out' is implicitly declared.
/path/to/file.sv:8: Warning: Identifier `\bus.in' is implicitly declared.

And the code written by Yosys has no knowledge of any bus.in or bus.out in bus_master.

/* Generated by Yosys 0.33+65 (git sha1 3319fdc46, g++ 12.2.0-14 -fPIC -Os) */

module bus_if();
endmodule

module bus_master(bus);
  inout bus;
  wire bus;
endmodule

module top(din);
  wire \bus.in ;
  input din;
  wire din;
  assign \bus.in  = din;
endmodule