Mario Larouche

compiler directive not showing in syntax_tree

2

The following single line verilog file: ``` `timescale 1 ns / 1 ps ``` produce the following syntax tree: ``` SourceText UnsignedNumber Token: '1' @ line:1 TimeUnit Keyword Token: 'ns'...

thread 'main' has overflowed its stack

2

The piece of verilog code below is causing the parser to exit with: > thread 'main' has overflowed its stack. I tried increasing the stack up to 64M without any...

Assuming the follow system verilog code: ``` `timescale 1ns/1ps interface net_interface; wire interface_wire; endinterface module example ( input wire port_input_wire ); net_interface iface_inst(); assign iface_inst.interface_wire = port_input_wire; endmodule module net_locations_testbench;...

variable_drivers_group and variable_loads_group reject my loads() and drivers() assignment.

1

I am working on traversing the design and setting the loads() and drivers() for nets and variables. Since this is not already currently supported (see issue #1101). I keep getting...