hierarchical reference to an interface wire not resolved during elaboration

[mlr11]

Assuming the follow system verilog code:

`timescale 1ns/1ps

interface net_interface;
  wire interface_wire; 
endinterface

module example (
  input wire port_input_wire
);

  net_interface iface_inst();
  assign iface_inst.interface_wire = port_input_wire;

endmodule

module net_locations_testbench;

  reg tb_input;

  example dut (
      .port_input_wire(tb_input)
  );
  
  // Access to interface net
  initial begin
    $monitor("Interface wire: %b", 
             dut.iface_inst.interface_wire);
  end
endmodule

The reference to dut.iface_inst.interface_wire has an ActualGroup of null after elaboration.

The assignment inside the module is correctly resolved but not the one using hierarchical path. I see the 3 components of the hierarchical path but only the dut part has been resolved

This is what uhdm-dump produces for this example for the hier_path reference:

        \_hier_path: (dut.iface_inst.interface_wire), line:27:14, endln:27:43
          |vpiParent:
          \_sys_func_call: ($monitor), line:26:5, endln:27:44
          |vpiActual:
          \_ref_obj: (dut), line:27:14, endln:27:17
            |vpiParent:
            \_hier_path: (dut.iface_inst.interface_wire), line:27:14, endln:27:43
            |vpiName:dut
            |vpiActual:
            \_module_inst: work@example (work@net_locations_testbench.dut), file:/home/mario/Projects/cayenne/tests/intfnet/intfnet.sv, line:20:3, endln:22:5
          |vpiActual:
          \_ref_obj: (iface_inst), line:27:18, endln:27:28
            |vpiParent:
            \_hier_path: (dut.iface_inst.interface_wire), line:27:14, endln:27:43
            |vpiName:iface_inst
          |vpiActual:
          \_ref_obj: (work@net_locations_testbench.interface_wire), line:27:29, endln:27:43
            |vpiParent:
            \_hier_path: (dut.iface_inst.interface_wire), line:27:14, endln:27:43
            |vpiName:interface_wire
            |vpiFullName:work@net_locations_testbench.interface_wire
          |vpiName:dut.iface_inst.interface_wire

Elaboration should resolve the hier_path reference to the actual net inside the interface.