mlabaf2

yes the problem was clen_t. thanks

thanks for response. I added some new in and out in FuOutput and FunctionUnitInput to have newer in/out in class Alu but I do not have access to them in...

Thank you for responses. what is the name if issue module? where is the source of input signals of Rob and where is the instance of Rob? I want to...

> For issue module, you can see `Scheduler` and `IssueQueue`. > > All these modules you mentioned are in a module (or submodules of that) named `Backend`. Have you ever...

thanks for your help when I "make ARCH=riscv64-xs" I received below error: "make: *** No rule to make target '/Makefile.app'. Stop" what does "make ARCH=riscv64-xs" exactly do? also, what does...

Another question is which .scala file call class Alu in Alu.scala file? I cannot find it to trace the mentioned error message...

thanks solved

Again I make verilog and problem fixed. Is it neccesary each time we change code, both make verilog and then make emu?

> We may publish our design documents shortly, but IO connection may not be available in the first edition. Is IO connection available for previous version of XiangShan?

> And I actually wonder why you want to change XLEN to 128. I want to add capability for memory protection which its length is 128 , like Cheri. What...