Michał Kopeć
Michał Kopeć
So Kaby Lake FSP is built without TXT support, so TXT init in coreboot fails, because FSP is expected to execute BIOS ACM Acheck function. Amberlake does not work presumably...
Did a cleanup of everything and squashed it into 1 commit. Fixed HDA config and prepared a nice commit message for upstream.
I solved the ME bootloop issue by adding me_state_counter to the CMOS settings. coreboot doesn't do the correct global reset needed after the ME enable HECI command, so a power...
Added the revision that was merged upstream and enabled CI builds. Any further features will be developed in subsequent PRs.
> How did you check the PCIe x16 slot? Plugged in a GPU (Radeon HD 4550), it didn't appear in `lspci` at all. Didn't investigate further yet
Finally got the HWM to work ^^ The EC actually has 6 "logical" TMPINs and extra temperature source select registers in Bank 2 that map physical and external sources to...
Turns out the two PCIe x1 slots work - at least with an NVMe SSD via an adapter. It's only the ASM1061 based SATA card that I was testing before...
Hi @Krakonos ! I think the biggest issue I never got resolved is the shutdown problem. I guess there is something missing on the SuperIO side. And there's also a...
We're after another rebase, maybe it's worth checking if the issue is fixed now, on the latest codebases?
Closing as fixed by https://github.com/Dasharo/edk2/pull/278 and https://github.com/Dasharo/coreboot/pull/782