Dasharo
Lenovo thinkcentre m700/add mainboard
Works:
- serial console on rear port
- SATA
- USB 2 / 3
- Video init via libgfxinit
- Built-in Realtek Ethernet
- Onboard TPM 1.2
- PCIe x16 slot
- PCIe x1 ports
Does not work:
- Shutdown
Not tested:
- PS/2 KB+M ports
- Audio
- S3 suspend
How did you check the PCIe x16 slot?
Plugged in a GPU (Radeon HD 4550), it didn't appear in lspci at all. Didn't investigate further yet
Finally got the HWM to work ^^ The EC actually has 6 "logical" TMPINs and extra temperature source select registers in Bank 2 that map physical and external sources to logical TMPINs.
Ended up having to add so much on top of the generic ITE EC code, that I should probably just add a separate EC implementation for IT8625E specifically.
Turns out the two PCIe x1 slots work - at least with an NVMe SSD via an adapter. It's only the ASM1061 based SATA card that I was testing before that doesn't work for some reason (same card works fine in the x16 slot)
@mkopec ASMedia cards are very picky... I wouldn't pay much attention to them unless you really need them.
Hi! I'm working on M700 for a home server and since I found schematics for the MB, I decided to give coreboot a try. Found this branch, it already saves me a bunch of work - I rebased most of the work onto the mainline coreboot and can boot seabios and subsequently an OS just fine. I wonder if you are still interested in the work?
I'm currently facing a few issues and I wonder if you have any pointers I should look into. My goals:
- Coffeelake support (worked out of the box, at least with i3-8100 - which is apparently is rebranded kaby lake silicon?).
- PCIe bifurcation (I believe I should just tell the init code to initialize 3 PCIe ports instead of one x16, but I don't know how to put that into the devicetree.
- UEFI payload (currently I only managed to get seabios to work, but I didn't do any extra work there)
- Smooth power on/off cycle (currently the board doesn't power off cleanly)
If I get it to a working state, I'd like to push it to mainline coreboot. @mkopec Are you OK with that, as the original author?
Cheers!
Hi @Krakonos !
I think the biggest issue I never got resolved is the shutdown problem. I guess there is something missing on the SuperIO side. And there's also a problem with S3 sleep, in my testing the power LED always stayed on and on resume it would just do a clean boot. My guess is this is also related to the SuperIO, could also be related to UEFIPayload.
Coffeelake support (worked out of the box, at least with i3-8100 - which is apparently is rebranded kaby lake silicon?).
Yeah, I've been running an i3-8100 myself for some months now, got one for upgraded iGPU for better transcoding in jellyfin. Has been running without problems, just needed to set the Mainboard supports Coffee Lake CPU Kconfig option.
PCIe bifurcation (I believe I should just tell the init code to initialize 3 PCIe ports instead of one x16, but I don't know how to put that into the devicetree.
The CPU PCIe port (the top x16 slot) is configured by physical straps (pins CFG[0:15]), so it can't be easily reconfigured. I know it's possible to work around this by masking / shorting the right pads on the CPU itself, but I've never tested this.
With PCH PCIe ports you could change these using soft straps (bits in the flash descriptor), but of course this board only has x1 PCH ports so they're sadly useless here.
UEFI payload (currently I only managed to get seabios to work, but I didn't do any extra work there)
I've been running UEFIPayload for some time, no major issues apart from the aforementioned S3 problem.
If I get it to a working state, I'd like to push it to mainline coreboot. @mkopec Are you OK with that, as the original author?
I actually submitted a (WIP) change to coreboot a while back, but didn't get around to finishing it because, well, I've been using my M700 as a homeserver and I kind of depend on it working now 😅 Here's the CL: https://review.coreboot.org/c/coreboot/+/64456 The changes need a rebase and there's some unresolved comments to be addressed.
Feel free to push the rebased code upstream, just please keep me as (co-)author in the commits :)
I think the biggest issue I never got resolved is the shutdown problem. I guess there is something missing on the SuperIO side. And there's also a problem with S3 sleep, in my testing the power LED always stayed on and on resume it would just do a clean boot. My guess is this is also related to the SuperIO, could also be related to UEFIPayload.
I'll check it out. TBH I did drop one of the SuperIO patches, as it has macro conflicts with the current codebase and I decided it isn't critical for now.
The CPU PCIe port (the top x16 slot) is configured by physical straps (pins CFG[0:15]), so it can't be easily reconfigured. I know it's possible to work around this by masking / shorting the right pads on the CPU itself, but I've never tested this.
Actually, I grounded (they are coveniently on pins 29 and 33 on JXDP1, right next to the CPU socket) the CFG[5] and CFG[6] pins according to the documentation, this should yield x8x4x4. I expected even the original bios would either error out or initialize 8x only and leave out the rest. However, nothing changed and the port still shows as 16x (but I don't have any 16x card at hand to test and don't feel like taking apart my workstation).
I tried enabling those by:
device pci 01.1 on # PEG
register "PcieRpEnable[1]" = "1"
register "Peg1MaxLinkWidth" = "Peg1_x4"
end
device pci 01.2 on # PEG
register "PcieRpEnable[2]" = "1"
register "Peg2MaxLinkWidth" = "Peg1_x4"
end
Unfortunately, it results in:
[DEBUG] PCI: 00:01.0 subordinate bus PCI Express
[DEBUG] PCI: 00:01.0 [8086/1901] enabled
[INFO ] PCI: Static device PCI: 00:01.1 not found, disabling it.
[INFO ] PCI: Static device PCI: 00:01.2 not found, disabling it.
However, there is mention of bifurcation in:
./src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
Also, I read somewhere that CFG[5:6] are supposed to be read by bios and bios then sets up the PCIe accordignly. This leads me to believe BIOS should set it up and the CFG[5:6] is possibly irrelevant. At least it seems to be not enough by itself.
I've been running UEFIPayload for some time, no major issues apart from the aforementioned S3 problem.
Good to know it should work. Is there any specific configuration one needs to do to make edk2 work? This is actually the first time for my working with tianocore/edk2 (and with coreboot anyway).
I actually submitted a (WIP) change to coreboot a while back, but didn't get around to finishing it because, well, I've been using my M700 as a homeserver and I kind of depend on it working now 😅 Here's the CL: https://review.coreboot.org/c/coreboot/+/64456 The changes need a rebase and there's some unresolved comments to be addressed.
Great, I see you also split the superio work into a different patchset. I'll check it out and move my changes there.
Looking at the PR there it seems you have some documentation to the IT8625E chipset? i didn't really find much, so any help would be appreciate. however, the schematics for the board contain all the GPIO functions and power sequencing (although not necessarily easy to read...)
Feel free to push the rebased code upstream, just please keep me as (co-)author in the commits :)
Absolutely. We'll see if I'll have enough motivation to finish.