meheff

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Add partial product multiply IR op

@grebe

Map channels to nodes in package

We do have a similar mapping for register -> registerWrite/Read nodes. This is maintained by code in Block::AddRegister and BlockRemove and overrides of AddNode and RemoveNode. However the channel map...

Map channels to nodes in package

@hongted

In JIT create a function per operation

This has been fixed for a while

Outlining pass

Interesting! It'd be a good exercise to run such an algorithm on our benchmarks and examples in which we might know there is benefit to outlining and see what pops...

Run generated verilog through verilog formatter

@taktoa This will cause a wrinkle in Verilog line tracking. I think it can be handled by analyzing the preformatted and postformatted Verilog and mutating the LineInfo accordingly. I imagine...

`std::find_index` does not lower efficiently

Here's an updated shot of the optimized IR graph from head. The array operations are gone with the addition of array_simplification_pass: https://github.com/google/xls/blob/main/xls/passes/array_simplification_pass.h ![new_find_index](https://user-images.githubusercontent.com/24232157/86654101-8eceae80-bf9a-11ea-9afd-5fcd1cb3aa9a.png)

Check whether fuzzer is still leaking, consider porting to C++

I'm guessing this is no longer an issue as many of the parts of the fuzzer have been ported over to C++ and we don't see ooms any more.

Create array shifting op?

Agree that an IR-level cast might be a good way to handle this. We'd just have to define a reasonable mapping between types. Hopefully that would match up with the...

Generate packed arrays via VAST codegen

Motivating example, consider an array of XLS type bits[16][3][2]. Currently this is declared as an unpacked array like so: ``` wire [15:0] foo[2][3]; ``` We should emit this as: ```...