meheff
meheff
Procs add a couple new relevant features relative to functions: state and channels. Exercising state and channels will require generating a random number (0 or more) inputs for each channel,...
Other useful features to have: * non-blocking receives * random FIFO depths (for proc networks)
Relevant bug on adding the necessary support to the Verilog simulation infrastructure: https://github.com/google/xls/issues/694
A couple other necessary/desirable features for proc fuzzing * Extend crasher format to support description of values on inputs channels * Improve proc support in the ir minimizer. This could...
fyi @vincent-mirian-google
[crasher_0d47.tar.gz](https://github.com/google/xls/files/5647764/crasher_0d47.tar.gz)
The additional metrics you pointed to in `BlockMetricsProto` (https://github.com/google/xls/commit/6652da40ee3c419a7bd1b265bada649727e45f6b#diff-930822aa60ed73921e227ad1698f2ef94cbba6cef9d6adabd550f19d0b181a7eR20) are generated from XLS internal analysis and not scraped from EDA tools. We will probably want some easy way to distinguish...
Below is a related internal discussion about a "prove" op which behaves like an assume but requires that the compiler itself prove the condition. This can be used to verify...
My slight preference would be to spell out Select fully.
FYI @hongted @taktoa