matlupi

Resolve "Rejected valid signal name"

6

Close #2076: add `analog` as potential AMS-dialect word in parser according to https://github.com/chipsalliance/verible/issues/2076#issuecomment-1919763868

**Describe the bug** The syntax checker rejects properties with the disable iff defined before the sampling event in a property. **To Reproduce** `test.sv` ```systemverilog module test; logic clk; logic rst;...

Rejected valid signal name

4

**Describe the bug** Short summary. **To Reproduce** ```bash verible-verilog-lint test.sv ``` with `test.sv` ```systemverilog module test; logic analog; endmodule ``` **Actual behavior:** Rejects valid syntax ``` test.sv:2 9-14 syntax error...

Insufficient forbidden-macro documentation

1

**Describe the bug** Description of `[forbidden-macro]` is insufficient. **Actual vs. expected behavior** "Checks that no forbidden macro calls are used." It is not clear what is a forbidden macro and...

Event triggering not recognised as valid syntax

5

**Describe the bug** There is a syntax error at the -> token. **To Reproduce** The minimized test case (test.sv): ```systemverilog module foo(input clk); event a; always @(posedge clk) -> a;...

The software crashes whenever I try to resize a window using a key combination or using the dropdown menu from the status bar. Versions: - MacBook Pro 13 M2 2022...

**Describe the bug** Case formatting of structure signals is not checked. **Test case (preferably reduced)** ```systemverilog module test(); typedef struct packed { logic OutSelectL; logic OutSelectC; } channel_cfg_t; endmodule ```...

**Describe the bug** Valid syntax is rejected **To Reproduce** Run ``` verible-verilog-syntax test.sv ``` `test.sv` as follows ```systemverilog interface t_interface; endinterface package test; typedef virtual t_interface t_vif_array []; endpackage ```...

parser refuses bit-selection of concatenation

1

**Describe the bug** The code below raises an error but is valid according to the LMR **To Reproduce** ```systemverilog class test; bit [31:0] pattern; constraint pattern_c { foreach (pattern[i]) if...

invalid-system-task-function not checked if multiple ifdefs are present in file

3

**Describe the bug** The rule `[invalid-system-task-function]` is not reported if the file contains multiple `ifdefs` **Test case (preferably reduced)** ```systemverilog module test; logic a; logic clk; `ifdef A c `ifndef...