Event triggering not recognised as valid syntax

[matlupi]

Describe the bug

There is a syntax error at the -> token.

To Reproduce

The minimized test case (test.sv):

module foo(input clk);
  event a;

  always @(posedge clk)
    -> a;
endmodule

Include any options used.

>> verible-verilog-syntax ../test.sv
../test.sv:5:5-6: syntax error at token "->"

Actual behavior:

The valid syntax is rejected

Expected behavior

In SystemVerilog-2017 Standard (LRM), section 15.5.1. Syntax 15-1

event_trigger ::= 
 -> hierarchical_event_identifier ;
| ->> [ delay_or_event_control ] hierarchical_event_identifier ;

[Lightborne]

Hello, I am new to how verible development works - I see tgorochowik added this to the release roadmap above. What does that mean in terms of an ETA for a release?

Also, are there any known workarounds?

[Lightborne]

Hello @tgorochowik - still wondering if this bug is on the roadmap to be fixed.

[tgorochowik]

Hi @Lightborne it most definitely is! I cannot provide any ETA at this moment though. Would you be interested in looking into this yourself and submitting a PR?

[corco]

@Lightborne I don't have the issue when decorating the always block in a begin/end. Could that be a workaround?

I have very few event in my codebase, if you can confirm it only fails on naked always block, it would help narrow the issue.

The following two cases passes:

module foo (
    input clk
);
  event a;

  always @(posedge clk) begin
    ->a;
  end
endmodule

module foo(input clk, b);
  event a;

  always @(posedge clk)
    if (b)
      -> a;
endmodule

[Lightborne]

@corco - wrapping in begin/end is a good workaround. Thanks!