Matt Liberty
Matt Liberty
The core area is defined by the bbox of all the rows in the design. I'm not sure what "placement boundary" is exactly.
@gatecat is there anything he we can resolve or should we just close?
OR works with a flat or hierarchical Verilog. Which one you load is up to your flow and isn't an OR issue per se.
we.tl does not work - it seems to require an account. There is no actionable test case here.
I managed to download it but it is a just a bunch of files and not a reproducible test case (there is no script to invoke). This is not in...
Not currently though we have some work underway that could allow it in the future.
That work stalled with a departure so no progress
This is a large project and will take a while. That is a piece of the solution but has no direct user benefit by itself.
Thanks for writing this up. A new comer doesn't have to implement every check in order to contribute. Ticking any box is helpful.
@rovinski in order to talk about access points we would have to run pin_access. This can only happen after macro placement at the earliest. How are you intending for this...