The-OpenROAD-Project
write_verilog command and hierarchy in a netlist
Hi, Does the write_verilog command in openroad have a switch for keeping hierarchy in a netlist? I used the read_verilog command in openroad to read a top level netlist file that instantiates two modules, but when i tried to write it out using write_verilog, a flattened netlist was generated. Is it possible to keep the hierarchy of a netlist in openroad?
Thanks, Ted
Not currently though we have some work underway that could allow it in the future.
Hi, is there any progress on this ?
I would like to try to bring-up Openroad on a commercial PDK after we tape-out with commercial tool. The thing is that our design is modular in the sense that it consists of multiple IPs. Each IP has its own UVM bench, and that binds to the ports of the IPs. On top level bench, we instantiate the individual IP benches. Then in synthesis, we dont_touch ports of each IP, so we keep the same signals and the UVM bench can bind also on top level GLS. That works OK on post-syn GLS. We then provide this "dont touch list" also to PnR to be sure that post-PnR netlist will preserve the sub-IP ports. This-way we can simulate sign-off SDF annotated top level netlist with each sub-IP having its bench checking its functionality with full timing across corners.
Without presrving the hierarchy in the post-pnr netlist, we are unable to simulate the netlist in our bench.
Could you maybe give me some pointers to place in the code where I should start looking if I wanted to implement this ?
Some recent work was added in https://github.com/The-OpenROAD-Project/OpenROAD/pull/4800. I think there's still quite a bit to go before supporting full hierarchy though.
This is a large project and will take a while. That is a piece of the solution but has no direct user benefit by itself.