Torsten Maehne

See also issue #1280.

Could you describe a use case where this transparency would be useful? Indeed, there are case, where it is sensible to place components on top of each other in Logisim,...

I agree, the actual rule is that it must be a legal identifier in VHDL and Verilog so that the name can be used without modification during the netlisting. A...

@Juan-Gg: Thanks for raising the issue! For sure, the documentation is outdated. Even some images are currently missing:  @BFH-ktt1 merged improvements to the chronogram from @kevinawalsh's [holy cross fork](https://github.com/kevinawalsh/logisim-evolution)....

@Oren14Dani: Thanks for your willingness to pick up this issue! When you are at it: Would you mind to also have a look at related issues #1605 and #1606? I...

Using a button as clock source is always risky when implementing it on FPGA due to bouncing. We routinely expose our students to this problem to train them to use...

@BFH-ktt1: Could you please provide feedback on @dxhisboy additional remarks?

In general, Logisim-evolution already allows you to choose the clock edge to be used by a flip-flop or register using the "Trigger" property. Registers provide you with a "WE" input...

@Alice-Cheshire: Please check `Help -> User's Guide -> Guide to Being a Logisim User -> Additional features -> Wire colors` for an explanation of the different wire colours. We could...

Thanks for your feedback @davidhutchens. Personally, I would like to see an adjustment to Verilog/VHDL conventions for consistency reasons even though I agree that there's also Logisim's history to be...